FOC Timing Simulator
The FOC Timing Simulator provides an interactive visualization of a 3-phase inverter circuit and PWM timing chart for Field-Oriented Control motor drives. It displays center-aligned and edge-aligned PWM waveforms, dead time intervals, ADC trigger points, current waveforms, and the FOC execution pipeline — all synchronized to a movable cursor. Free, no signup required.
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What is FOC Timing?
Field-Oriented Control (FOC) timing refers to the precise synchronization between PWM signal generation, ADC current sampling, encoder position reading, and the FOC computation pipeline in a 3-phase motor drive. A typical FOC cycle at 20 kHz (50μs period) must complete ADC sampling at the PWM valley, read encoder position, perform Clarke/Park transforms, run PI controllers, and update PWM duty cycles — all within a single PWM period. Correct timing ensures accurate current measurement (by sampling when low-side MOSFETs are ON), minimal torque ripple, and stable motor control. Dead time (0.5–3μs) between high-side and low-side switching prevents shoot-through that could destroy the inverter.
How to Use the FOC Timing Simulator
- Drag the position slider to move the cursor across the timing chart and observe how circuit states change
- Adjust duty cycle (20–80%) to see how PWM pulse widths vary for each phase
- Change dead time (0.5–3μs) to visualize the protection interval between high-side and low-side switching
- Toggle between center-aligned and edge-aligned PWM modes to compare timing behavior
- Enable auto-play to watch the full animation cycle showing sinusoidal modulation
Frequently Asked Questions
Why is center-aligned PWM preferred for FOC?
Center-aligned PWM creates a symmetrical triangle counter (0→peak→0), which produces lower current ripple and creates natural sampling points at the valley where all low-side MOSFETs are ON. This allows simultaneous shunt current measurement for all 3 phases. Edge-aligned PWM has only one direction (0→peak), resulting in higher ripple and fewer optimal sampling points.
What is dead time and why is it necessary?
Dead time (typically 0.5–3μs) is a protective interval where both the high-side and low-side MOSFETs in a half-bridge are OFF. Without dead time, switching delays could cause both MOSFETs to be ON simultaneously (shoot-through), creating a short circuit from V+ to GND that can destroy the power stage. The dead time must be longer than the MOSFET turn-off delay.
Why does the ADC trigger at the PWM valley?
At the valley (counter=0 in center-aligned mode), all low-side MOSFETs are ON and all high-side MOSFETs are OFF. This is the optimal moment to sample shunt resistor currents because the current path through the low-side MOSFET and shunt resistor is stable, giving the most accurate current reading with minimal switching noise.
How long does one FOC computation cycle take?
A typical FOC cycle on modern MCUs (e.g., TI C2000, Infineon Aurix) takes approximately 20–30μs, which includes: ADC conversion (~2μs), Clarke/Park transforms (~3μs), PI current controllers (~5μs), inverse Park transform (~3μs), Space Vector Modulation (~3μs), and PWM register update (~2μs). This must fit within the 50μs PWM period at 20 kHz.
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