Parasitic Capacitance Calculator
The Parasitic Capacitance Calculator computes parasitic capacitance for five common PCB geometries: microstrip, stripline, via, parallel traces, and pad-to-ground. Each geometry includes an interactive SVG cross-section diagram that updates dimension labels in real time. Supports substrate presets (FR-4, Rogers 4350B) and mm/mil unit switching. Free, no signup required.
PCB Geometry
Trace on surface layer above a ground plane
Substrate Preset
Cross-Section Diagram
Results
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What is Parasitic Capacitance in PCBs?
Parasitic capacitance is unintended capacitance that exists between conductors on a printed circuit board. Every PCB trace, via, and pad forms a capacitor with nearby conductors and ground planes through the dielectric substrate. At high frequencies (above 100 MHz), these parasitic capacitances — typically ranging from 0.1 pF to 5 pF — can degrade signal integrity, cause crosstalk between adjacent traces, and alter impedance matching. Accurate calculation of parasitic capacitance is essential for reliable high-speed digital design, RF circuit layout, and EMC compliance.
How to Use the Parasitic Capacitance Calculator
- Select the PCB geometry type (microstrip, stripline, via, parallel traces, or pad-to-ground)
- Choose a substrate preset (FR-4, Rogers 4350B, etc.) or enter custom dielectric properties
- Enter physical dimensions in mm or mil (toggle between unit systems as needed)
- View the interactive cross-section diagram with your dimensions
- Read the calculated capacitance, impedance, and propagation delay results
Frequently Asked Questions
What is a typical parasitic capacitance value for a PCB via?
A standard 0.3 mm drill / 0.6 mm pad via through 1.6 mm FR-4 has approximately 0.3–0.5 pF of parasitic capacitance. High-density designs with smaller vias (0.2 mm drill) or thinner substrates can achieve less than 0.2 pF. These values become significant at frequencies above 1 GHz.
How does parasitic capacitance affect signal integrity?
Parasitic capacitance creates low-impedance paths at high frequencies, causing signal reflections, ringing, and increased crosstalk between adjacent traces. In high-speed designs (DDR4/5, PCIe, USB 3.x), even 0.5 pF of unaccounted capacitance can degrade eye diagram openings and increase bit error rates.
What is the difference between microstrip and stripline parasitic capacitance?
Microstrip traces run on the surface with air above and dielectric below, resulting in a lower effective dielectric constant and typically 30–40% less capacitance per unit length than stripline. Stripline traces are fully embedded in dielectric between two ground planes, producing higher and more predictable capacitance but better shielding from external interference.
How can I reduce parasitic capacitance on a PCB?
To reduce parasitic capacitance: use thicker substrates (increases distance to ground plane), choose lower-εr materials (Rogers vs FR-4), minimize pad sizes, increase trace spacing for coupled lines, use anti-pads around vias, and avoid running traces parallel to each other over long distances. Each technique trades off against other design constraints like board size and layer count.